The process of etching MRAM cell for array connection is challenging because of the possibility of over-etching (OE) tantalum (Ta) in the top electrode of the magnetic tunnel junction (MTJ), thereby outgassing the Ta residue defect and impacting device performance during electrical testing (ET).
A need therefore exists for a device with a capping layer to achieve a balanced etch for both MRAM array and logic area to solve the Ta residue defect for a cleaner ET, and for enabling methodology.